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DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
August 2005
XR68C92/192
DESCRIPTION
The XR68C92/192 is a Dual Universal Asynchronous Receiver and Transmitter with 8 (XR68C92) / 16 (XR68C192) bytes transmit and receive FIFO. The XR68C92/192 is a pin-to-pin compatible and an improved version of the XR68C681 and the Philips SCC68692 UART with faster data access and other additional features. The operating speed of the receiver and transmitter can be selected independently from a table of eighteen fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock input. The XR68C92/192 provides a power-down mode in which the oscillator is stopped but the register contents are retained. The XR68C92/192 is fabricated in an advanced CMOS process to achieve low power and high speed requirements.
FEATURES
Added features in devices with top marking of "D2" and newer: * 5 volt tolerant inputs * Pin to pin compatible and improved version of the SCC68692 and XR68C681 * Enhanced Multidrop mode operation with separate storage for address and data tags (9th bit) * 8 Bytes transmit/receive FIFO (XR68C92) *16 Bytes transmit/receive FIFO (XR68C192) * Standard baud rates from 50bps to 230.4kbps * Non-standard baud rate of up to 1Mbps * Transmit and Receive trigger levels * Watch dog timer * Programmable clock source for receiver and transmitter of each channel * Single interrupt output * 7 Multipurpose inputs, 8 Multipurpose outputs * 2.97 to 5.5 volt operation * Programmable character lengths (5, 6, 7, 8) * Parity, framing, and over run error detection * Programmable 16-bit timer/counter * On-chip crystal oscillator * Power down mode
PLCC Package
41 -IACK VCC N.C. IP1 IP3 IP4 IP5 IP2 40 39 -CS 38 -RESET 37 36 35 XTAL2 XTAL1 RXA N.C. TXA OP0 OP2 OP4 OP6 34 33 32 31 30 29 D1 18 D3 19 D5 20 D7 21 GND 22 N.C. 23 -INT 24 D6 25 D4 26 D2 27 D0 28 A2 A1 A0
44
43
A3 IP0 R/-W
7 8 9
-DTACK 10 RXB N.C. TXB OP1 OP3 OP5 OP7 11 12 13 14 15 16 17
XR68C92 XR68C192
ORDERING INFORMATION
Part number Package Operating temperature Device Status
XR68C92CP XR68C92CJ XR68C92CV XR68C92IP XR68C92IJ XR68C92IV XR68C192CJ XR68C192CV XR68C192IJ XR68C192IV
40-Lead 44-Lead 44-Lead 40-Lead 44-Lead 44-Lead 44-Lead 44-Lead 44-Lead 44-Lead
PDIP PLCC LQFP PDIP PLCC LQFP PLCC LQFP PLCC LQFP
0 C to + 70 C 0 C to + 70 C 0 C to + 70 C -40 C to + 85 C -40 C to + 85 C -40 C to + 85 C 0 C to + 70 C 0 C to + 70 C -40 C to + 85 C -40 C to + 85 C
Active. See the XR68C92CV for new designs. Active Active Active. See the XR68C92IV for new designs. Active Active Active Active Active Active
Rev. 1.33 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017
42
6
5
4
3
2
1
XR68C92/192
Package Description 40 Pin DIP Package 44 Pin LQFP Package
-IACK 35
VCC
VCC
IP1
IP3
IP4
IP5
A2
A1
44
43
42
41
40
39
38
37
36
A1 IP1 A2 A3 IP0 R/-W -DTACK RXB TXB OP1 OP3 OP5 OP7 D1 D3 D5 D7 GND
3 4 5 6 7 8
38
IP5
A3 IP0 R/-W -DTACK RXB TXB 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 -CS -RESET XTAL2 XTAL1 RXA TXA OP0 OP2 OP4 OP6 N.C.
37 -IACK 36 IP2
35 -CS 34 -RESET 33 XTAL2 XTAL1
9 10 11 12 13 14 15 16 17 18 19 20
XR68C92 XR68C192
32 31 30 29 28 27 26 25 24 23 22 21
XR68C92 XR68C192
34
IP3
2
39
IP4
A0
A0
1
40
VCC
IP2
28 27 26 25 24 23
OP1
RXA TXA OP0 OP2 OP4
OP3 OP5 OP7 N.C.
12
13
14
15
16
17
18
19
20
21 D2
OP6 D0 D2 D4 D6 -INT
GND
GND
-INT
D6
D4
D1
D3
D5
Rev. 1.33
2
D7
D0
22
XR68C92/192
Block Diagram
Channel A Data Bus Buffers & Control Logic
Transmit FIFO Registers Transmit Shift Register
TXA
D0-D7 R/-W -DTACK -IACK -RESET
Flow Control Logic Receive FIFO Registers Receive Shift Register
RXA
Watch Dog Timer
A0-A3 -CS
Register Select Logic
Flow Control Logic
Interconnect Bus Lines & Control Signals
Channel B
Transmit FIFO Registers Transmit Shift Register
TXB
Interrupt Control Logic
Flow Control Logic Receive FIFO Registers Receive Shift Register
-INT
RXB
Watch Dog Timer
Flow Control Logic
XTAL1 XTAL2
Clock & Baud Rate Generator
OP0-OP7 MultiPurpose I/O Control Logic
IP0-IP5
Rev. 1.33
3
XR68C92/192
SYMBOL DESCRIPTION (* 44 pin LQFP)
Symbol 44 -RESET 38
Pin 40 34
44* 32
Signal type I
Pin Description
Master Reset (active low). A low on this pin will reset all the outputs and internal registers. The transmitter output and the receiver input will be disabled during reset time. Address select lines. To select internal registers. Interrupt acknowledge (active low). A low on this pin indicates that the CPU has received an interrupt. If not used, this pin should be tied to VCC. Data Transfer Acknowledge ( three-state active low output). A low on this pin indicates proper transfer of data between the CPU and XR68C92/192 during read, write and interrupt cycles. Chip select (active low). A low at this pin enables the data bus transfer operation. Bi-directional data bus. Eight bit, three state data bus to transfer information to or from the CPU. D0 is the least significant bit of the data bus and the first serial data bit to be received or transmitted. Read/Write strobe. When -CS is asserted, a high on this pin transfers the contents of the XR68C92/192 data bus to the CPU, and a low on this pin will transfer the contents of the CPU data bus to the addressed register. Interrupt output (open drain, active low) This pin goes low upon occurrence of one or more of eight maskable interrupt conditions (when enabled by the interrupt mask register). CPU can read the interrupt status register to determine the interrupting condition(s). This output requires a 10k ohms pull-up resistor. Crystal input 1 or external clock input. A crystal can be connected between this pin and XTAL2 pin to utilize the internal oscillator circuit. An external clock can be used to clock internal circuit and baud rate generator for custom transmission rates.
A0-A3
2,4, 6,7 41
1,3, 5,6 37
40,42, 44,1 35
I I
-IACK
-DACK
10
9
4
O
-CS
39
35
33
I
D0-D7
28,18 27,19 26,20 25,21 9
25,16 24,17 23,18 22,19 8
22,12 21,13 20,14 19,15 3
I/O
R/-W
I
-INT
24
21
18
O
XTAL1
36
32
30
I
Rev. 1.33
4
XR68C92/192
SYMBOL DESCRIPTION (* 44 pin LQFP)
Symbol 44 XTAL2 RXA, RXB 37 35,11
Pin 40 33 31,10
44* 31 29,5
Signal type O I
Pin Description Crystal input 2 or buffered clock output. See XTAL1. Serial data input. The serial information (data) received from serial port to XR68C92/192 receive input circuit. A mark (high) is logic one and a space (low) is logic zero.This input must be held at logic one when idle and during power down. Serial data output. The serial data is transmitted via this pin with additional start , stop and parity bits. This output will be held in mark (high) state during reset, local loop back mode or when the transmitter is disabled. Multi-purpose input or Channel A Clear-To-Send (-CTSA active low). If not used, this pin should be tied to VCC. Multi-purpose input or Channel B Clear-To-Send (-CTSB active low). If not used, this pin should be tied to VCC. Multi-purpose input or Channel B receive external clock input (received data is sampled on the rising edge of the clock) or Timer/Counter External clock input. If not used, this pin should be tied to VCC or GND. Multi-purpose input or Channel A transmit external clock input. The transmit data is clocked on the falling edge of the clock. If not used, this pin should be tied to VCC or GND. Multi-purpose input or Channel A receive external clock input. The received data is clocked on the rising edge of the clock. If not used, this pin should be tied to VCC or GND. Multi-purpose input or Channel B transmit external clock input. The transmit data is clocked on the falling edge of the clock. If not used, this pin should be tied to VCC or GND. Multi-purpose output. General purpose output or Channel A Request-To-Send (-RTSA active low). Multi-purpose output. General purpose output or Channel B Request-To-Send (-RTSB active low). Multi-purpose output. General purpose output or one of the
TXA, TXB
33,13
30,11
28,6
O
IP0
8
7
2
I
IP1
5
4
43
I
IP2
40
36
34
I
IP3
3
2
41
I
IP4
43
39
37
I
IP5
42
38
36
I
OP0
32
29
27
O
OP1
14
12
7
O
OP2 Rev. 1.33
31
28
26
O
5
XR68C92/192
SYMBOL DESCRIPTION (* 44 pin LQFP)
Symbol 44 Pin 40 Signal type Pin Description following functions can be selected for this output pin by programming the Output Port Confiuration Register bits 1,0; TxAClk1 -Transmit 1X clock. TxAClk16 -Transmit 16X clock RxAClk1 -Receive 1X clock OP3 15 13 8 O Multi-purpose output. General purpose output or one of the following functions can be selected for this output pin by programming the Output Port Confiuration Register bits 3,2; C/T -Counter timer output (Open drain output) TxBClk1 -Transmit 1X clock RxBClk1 -Receive 1X clock OP4 30 27 25 O Multi-purpose output. General purpose output or one of the following functions can be selected for this output pin by programming the Output Port Confiuration Register bit 4; -RxARDY -Receive ready signal (Open drain output) -RxAFULL - Receive FIFO full signal (Open drain output) OP5 16 14 9 O Multi-purpose output. General purpose output or one of the following functions can be selected for this output pin by programming the Output Port Confiuration Register bit 5; -RxBRDY - Receive ready signal (Open drain output) -RxBFULL - Receive FIFO full signal (Open drain output) OP6 29 26 24 O Multi-purpose output. General purpose output or Transmit A holding register empty interrupt (-TxARDY Open drain output). Multi-purpose output. General purpose output or Transmit B holding register empty interrupt (-TxBRDY Open drain output) Signal and power ground. Power supply input, 2.97V to 5.5V. No Connection.
44*
OP7
17
15
10
O
GND VCC N.C.
22 44 1,12 23,34
20 40 -
16,17 38,39 11,23
Pwr Pwr
Rev. 1.33
6
XR68C92/192
INTERNAL CONTROL LOGIC The internal control logic of the XR68C92/192 receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to control device operation. The internal control logic takes in the following inputs: * -CS, which is the XR68C92/192 chip-select; * R/-W which allows data transfers between the CPU and XR68C92/192via the data bus (D0 to D7); * four register-select lines (A0 through A3) which are decoded to allow access to the registers within the XR68C92/192; * -RESET (reset), which initializes or resets all outputs and internal registers. COMMUNICATION CHANNELS A AND B Each communication channel includes a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and each transmitter can be selected independently from the baud rate generator, the Counter/Timer (C/T), or from an external clock. The transmitter accepts parallel data from the CPU, converts it to a serial bit stream in the form of a character and outputs it on the Transmit Data output pin (TXA, TXB). The character consists of start, stop, and optional parity bits, The receiver accepts serial data on the Receive Data input pin (RXA, RXB), converts this serial input to parallel format, checks for a start bit, stop bit, parity bit (if any), framing error, overrun or break condition, and transfers the data byte to the CPU during read operations. TIMING LOGIC The timing logic consists of * a crystal oscillator, * a baud rate generator (BRG), * clock selector logic, and * a programmable 16-bit counter/timer (C/T). The crystal oscillator operates directly from a typical 3.6864 MHz crystal connected across the XTAL1 and XTAL2 inputs or from an external clock of the appropriate frequency connected to XTAL1. The XTAL1 clock serves as the basic timing reference for the baud rate generator, the C/T, and other internal circuits. The baud rate generator operates from the XTAL1 clock input and can generate 28 commonly used data communication baud rates (if a typical 3.6864MHz crystal or clock is used) ranging from 50 to 230.4kbps by producing internal clock outputs at 16 times the actual baud rate. In addition, other baud rates can be derived by connecting 16X or 1X clocks to multipurpose input port pins IP3 - IP6 that have alternate functions as receiver or transmitter clock inputs. Clock selector logic consists of the clock selector register (CSRA, CSRB), bits 0 & 2 of Mode Register 0 (MR0A, MR0B) and bit-7 of Auxilliary Control Register (ACR). These allow various combinations of these baud rates for receiver and transmitter of each channel. See Baud Rate Table on page 18 for more details. The programmable 16-bit counter/timer (C/T) can produce a 16X clock for other baud rates by counting down its programmed clock source. Users can program the 16 bit C/T within the XR68C92/192 to use one of several clock sources as its input. The output of the C/ T is available to the internal clock selectors and can also be programmed to appear at output OP3. In the timer mode, the C/T acts as a programmable divider and can generate a square-wave output at OP3. In the counter mode, the C/T can be started and stopped under program control. When stopped, the CPU can read its contents. The counter counts down the number of pulses stored in the concatenation of the C/T upper register and C/T lower register and produces an interrupt. This is a system-oriented feature that can be used to record timeouts when implementing various application protocols. INTERRUPT CONTROL LOGIC The following registers are associated with the interrupt control logic: * Interrupt Mask Register (IMR) * Interrupt Status Register (ISR) * Auxiliary Control Register (ACR) * Interrupt Vector Register (IVR) A single active-low interrupt output (-INT) can notify the CPU that any of eight internal events has occurred. These eight events are described in the discussion of the interrupt status register (ISR). User can program the interrupt mask register (IMR) to allow only certain conditions to cause -INT to be asserted while the CPU can read the ISR to determine all currently active interrupting conditions. When an active-low interrupt acknowledge signal (-IACK) from the CPU is asserted
Rev. 1.33
7
XR68C92/192
while the XR68C92/192 has an interrupt pending, the XR68C92/192 will place the contents of the interrupt vector register (IVR, address 0x0C) on the data bus and assert the data transfer acknowledge signal (-DACK). If the XR68C92/192 has no pending interrupt, it ignores the -IACK cycles. In addition, users can program the parallel outputs OP3 through OP7 to provide discrete interrupt outputs for the transmitters, the receivers, and the C/T. See 'Multi-purpose Outputs' section for details. DATA BUS BUFFER (D0 - D7) The data bus buffer provides the interface between the external and internal data buses. It is controlled by the internal control logic to allow read and write data transfer operations to occur between the controlling CPU and XR68C92/192 by way of the eight parallel data lines (D0 through D7). MULTI-PURPOSE INPUTS (IP0 - IP5) The states of the seven multi-purpose inputs (IP0 through IP5) can be read from the internal register IPR (address 0x0D). The bits in this register are the complements of the actual inputs - for example, if the IP0 is low, the corresponding bit in the IPR, bit-0 is a logic '1'. Each of these inputs also has an alternate control function capability. The alternate functions can be enabled/disabled on a bit-by-bit basis. The table below shows how each of these inputs is configured for its special function. Four change-of-state detectors are associated with inputs IP0, IP1, IP2, and IP3. If a high-to-low or low-tohigh transition occurs on any of these inputs, the corresponding bit in the input port change register (IPCR - address 0x04) will be set accordingly. The sampling clock of the change detectors is the XTAL1/ 96 tap of the baud rate generator, which is 38.4kHz if XTAL1 is 3.6864MHz. A new input level must be Input IP0 IP1 IP2 IP3 IP4 IP5 Function -CTSA -CTSB C/T Ext. Clk TxA Ext. Clk RxA Ext. Clk TxB Ext. Clk Programming Set MR2A bit-4 = 1 Set MR2B bit-4 = 1 Set ACR[6:4] = 000 Set CSRA[3:0] = 1110 or 1111 Set CSRA[7:4] = 1110 or 1111 Set CSRB[3:0] = 1110 or 1111 sampled on two consecutive sampling clocks to detect a change. Also, users can program the XR68C92/192 to allow a change of state in any of the inputs IP0 through IP3 to generate an interrupt to the CPU. See description of the Interrupt Status Register (ISR, address 0x05) for details. The IPCR bits are cleared when the CPU reads the register. Also see the Baud Rate Table on page 18. MULTI-PURPOSE OUTPUTS (OP0 - OP7) The eight output pins (OP0 - OP7) can either be used as general purpose outputs or can be used for alternate functions representing various conditions using - Mode Registers 1 and 2 (MR1A, MR1B, MR2A, MR2B) - Output Port Configuration Register (OPCR) - Set Output Port Register (SOPR), and - Reset Output Port Register (ROPR). OP0 and OP1: The output OP0 can function as the channel A requestto-send (-RTSA) output for either the transmitter (MR2A bit-5 = 1) or the receiver (MR1A bit-7 = 1). Note that only one of these bits should be set to '1' at a given time. See the description of the transmitter RTS and receiver RTS in the 'Transmitter' and 'Receiver' sections of this datasheet respectively. The output OP1 acts as the channel B request-to-send (-RTSB) output
XR68C92/192
200 - 500 k
XTAL1 Y1 3.6864MHz C1 22-47pF
XTAL2
C2 22-47pF
Figure 1: Crystal Connection
Rev. 1.33
8
XR68C92/192
and is controlled in a similar way by the channel B registers. OP2 - OP7: The other outputs (OP2 - OP7) are configured via the OPCR. Please see the description under the OPCR register for the details. CRYSTAL INPUTS (XTAL1 & XTAL2) If a crystal is used, it is connected between XTAL1 and XTAL2, in which case a capacitor of approximately 22 to 47 pF should be connected from each of these pins to ground (see Figure 1). If an external CMOS-level clock is used, the pin XTAL2 must be left open. RESET The XR68C92/192 can be reset by asserting the -RESET signal or by programming the appropriate internal registers. A hardware reset (assertion of -RESET) clears the following registers: * Status Registers A and B (SRA and SRB) * Interrupt Mask Register (IMR) * Interrupt Status Register (ISR) * Output Port Configuration Register (OPCR) RESET also performs the following operations: * Initializes the interrupt vector register (IVR) to 0x0F. * Places the outputs OP0 through OP7 in the high state * Places the counter/timer in counter mode * Places channels A and B in the inactive state with the transmitter serial-data outputs (TXA and TXB) in the mark (high) state. Reset commands can be programmed through the command registers to reset the receiver, transmitter, error status, or break-change interrupts for each channel. TRANSMITTER The transmitter converts the parallel data from the CPU to a serial bit stream on the transmitter output pin (TXA, TXB). It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least-significant bit is sent first. Data is shifted out the transmit serial data output pin (TXA, TXB) on the falling edge of the programmed clock source (XTAL1, NOTE: The terms assertion and negation will be used extensively to avoid confusion when dealing with a mixture of "active low" and "active high" signals. The term assert or assertion indicates that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. IP3 or IP5: see CSR bits 3:0). After the transmission of the stop bits, and a new character is not available in the transmit FIFO, the transmitter serial data output (TXA, TXB) remains high. Transmission resumes when the CPU loads a new character into the transmit FIFO. If the transmitter receives a disable command (CRA, CRB bits 3:2), it will continue operating until the character in the transmit shift register is completely sent out. Other characters in the FIFO are neither sent nor discarded, but will be sent when the transmitter is reenabled. TX RTS Control: Users can program the transmitter to automatically negate the request-to-send (RTS) output (alternate function of OP0 and OP1 for channels A and B respectively) on completion of a message transmission (using MR2A, MR2B bit-5). If the transmitter is programmed to operate with RTS control, the RTS output must be manually asserted before each message is transmitted. Also, the transmitter needs to be disabled after all the required data are loaded into the FIFO. Then, the RTS output will be automatically negated when the transmit-shift register and the TX FIFO are both empty. In automatic RTS mode, no more characters can be written to the FIFO after the transmitter is disabled. If auto clear-to-send (CTS) control is enabled (using MR2A, MR2B bit-4), the CTS input (alternate function of IP0 and IP1 for channels A and B respectively) must be asserted (low) in order for the character to be transmitted. If it gets negated (high) in the middle of a transmission, the character in the shift register is transmitted and the transmit data output (TXA, TXB) then remains in the marking state until CTSA, CTSB gets asserted again. The transmitter can also be forced to send a continuous low (space) condition by issuing the start-break command (see CRA, CRB bits 7:4). The state of CTS is ignored by the transmitter when it is set to send a break.
Rev. 1.33
9
XR68C92/192
A start-break is deferred as long as the transmitter has characters to send, but if normal character transmission is inhibited by CTS, the start-break will proceed. The start-break must be terminated by a stop-break or a TX disable + TX reset before normal character transmission can resume. The channel A and B transmitters are enabled for data transmission through their respective command registers (see CRA, CRB bits 3:2). The transmit FIFO trigger levels (see MR0A, MR0B bits 4 and 5) are used to generate an interrupt request to the CPU on the -INT pin. This is also reflected in the Interrupt Status Register, ISR bit-0 for channel A and bit-4 for channel B. This is different from the TxRDY bit in the status register. The TxRDY bit in the status register (SRA, SRB bit-2) indicates if the TX FIFO has at least one empty location. This can also be programmed to appear at the output pin OP6/OP7. The TxEMT bit (SRA, SRB bit-3) indicates if both the TX FIFO and the TX Shift Register are empty. The transmitter can be reset through a software command (CRA, CRB bits 7:4). If it is reset, operation ceases immediately and must be enabled through the command register before resuming operation. Reset also discards any characters in the FIFO. RECEIVER The channel A and B receivers are enabled for data reception through the respective channels command register (CRA, CRB bits 1:0). The channels receiver looks for the high-to-low (mark-to-space) transition of a start bit on the receiver serial-data input pin. If operating in 16X clock mode, the serial input data is resampled on the next 7 clocks. If the receiver serial data is sampled high, the start bit is invalid and the search for a valid start bit begins again. If receiver serial data is still low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals (at the theoretical center of the bit) until the proper number of data bits and the parity bit (if any) have been assembled and one stop bit has been detected. If an 1X clock is used, data is sampled at one bit time intervals throughout, including the start bit. Data on the receiver serial data input pin is sampled on the rising edge of the programmed clock source (XTAL1, IP4 or IP6: see CSR bits 7:4). In this process, the least significant bit is received first. The receiver buffer is composed of the FIFO (8/16 Rev. 1.33
10
locations in XR68C92/192 respectively) and a receive shift register connected to the receiver serial-data input. Data is assembled in the shift register and loaded into the bottom most empty FIFO location. If the character length is less than eight bits, the most significant unused bits are set to zero. If the stop bit is sampled as a 1, the receiver will immediately look for the next start bit. However, if the stop bit is sampled as a 0, either a framing error or a received break has occurred. If the stop bit is 0 and the data and parity (if any) are not all zero, it is a framing error. The damaged character is transferred to the FIFO with the framing error flag set. If the receiver serial data remains low for one-half of the bit period after the stop bit was sampled, the receiver operates as if a new start bit transition has been detected. If the stop bit is 0 and the data and parity (if any) bits are also all zero, it is a break. A character consisting of all zeros will be loaded into the the FIFO with the received-break bit (but not the framing error bit) set to one. The receiver serial-data input must return to a high condition for at least one-half bit time before a search for the next start bit begins. Also, at this time, the received break bit is reset. The receiver can detect a break that starts in the middle of a character provided the break persists completely through the next character time or longer. When the break begins in the middle of a character, the receiver will place the damaged character in the FIFO with the framing error bit set. Then, provided the break persists through the next character time, the receiver will also place an all-zero character in the FIFO with the received-break bit set. The parity error, framing error, overrun error, and received-break conditions (if any) set error and break flags in the status register at the received character boundary and are valid only when the receiver-ready bit (RXRDY) in the status register is set. The receiver-ready bit in the status register (SRA, SRB bit-0) is set whenever one or more characters are available to be read by the CPU. A read of the receiver buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are "popped" and new data can be added at the bottom of the stack by the receive shift register. The FIFO-full status bit (SRA, SRB bit-1) is set if all 8 (or 16) stack positions are filled with data. Either the receiver-ready
XR68C92/192
or the FIFO-full status bits can be selected to cause an interrupt (see MR1A, MR1B bit-6). In addition to the data byte, three status bits (parity error, framing error, and received break) are appended to each data character in the FIFO (overrun is not). By programming the error-mode control bit (MR1A, MR1B bit-5), status can be provided for "character" or "block" modes. In the "character" mode, the status register (SRA, SRB) is updated on a character-by-character basis and applies only to the character at the top of the FIFO. Thus, the status must be read before the character is read. Reading the character pops the data byte and its error flags off the FIFO. In the "block" mode, the status provided in the status register for the parity error, framing error, and received-break conditions are the logical OR of these respective bits, for all the data bytes in the FIFO stack since the last reset error command (see CRA, CRB bits 7:4) was issued. That is, beginning immediately after the last reset-error command was issued, a continuous logical-OR function of corresponding status bits is produced in the status register as each character enters the FIFO. The block mode is useful in applications requiring the exchange of blocks of information where the software overhead of checking each character's error flags cannot be tolerated. In this mode, entire messages can be received and only one data integrity check is performed at the end of each message. Although data reception in this manner has speed advantages, there are also disadvantages. If an error occurs within a message the error will not be recognized until the final check is performed. Also, there is no indication of which character(s) is in error within the message. Reading the status register (SRA, SRB) does not affect the FIFO. The FIFO is "popped" only when the receive buffer is read. If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exists, the contents of the FIFO are not affected, but the character previously in the shift register is lost and the overrunerror status bit will be set upon receipt of the start bit of the new overrunning character. To support flow control, a receiver can automatically negate and reassert the request-to-send (RTS) output (RX RTS control - see MR1A, MR1B bit-7). The request-to-send output (at OP0 or OP1 for channel A or B respectively) will automatically be negated by the Rev. 1.33
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receiver when a valid start bit is received and the FIFO stack is full. When a FIFO position becomes available, the request-to-send output will be reasserted automatically by the receiver. Connecting the request-tosend output to the clear-to send (CTS) input of a transmitting device prevents overrun errors in the receiver. The RTS output must be manually asserted the first time. Thereafter, the receiver will control the RTS output. If the FIFO stack contains characters and the receiver is then disabled, the characters in the stack can still be read but no additional characters can be received until the receiver is again enabled. If the receiver is disabled while receiving a character, or while there is a character in the shift register waiting for a FIFO opening, these characters are lost. If the receiver is reset, the FIFO stack and all of the receiver status bits, the corresponding output ports, and the interrupt request are reset. No additional characters can be received until the receiver is again enabled. LOOPBACK MODES Besides the normal operation mode in which the receiver and transmitter operate independently, each XR68C92/192 channel can be configured to operate in various looping modes (see MR2A, MR2B bits 7:6) that are useful for local and remote system diagnostic functions. AUTOMATIC ECHO MODE In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU-toreceiver communication continues normally but the CPU-to-transmitter link is disabled. LOCAL LOOPBACK MODE In this mode, the transmitter output is internally connected to the receiver input. The external TX pin is held in the mark (high) state in this mode. By sending data to the transmitter and checking that the data assembled by the receiver is the same data that was sent, proper channel operation can be assured. In this mode the CPU-to-transmitter and CPU-to-receiver communications continue normally. REMOTE LOOPBACK MODE In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU-toreceiver and CPU-to-transmitter links are disabled.
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This mode is useful in testing the receiver and transmitter operation of a remote channel. This mode requires the remote channel receiver to be enabled. MULTIDROP MODE - Enhanced with Extra A/D Tag Storage Users can program the channel to operate in a wakeup mode for Multidrop applications. In this mode of operation (set MR1A, MR1B bits 4:3 = 11), the XR68C92/192, as a master station channel connected to several slave stations (a maximum of 256 unique slave stations), transmits an address character followed by a block of data characters targeted for one or more of the slave stations. The channel receivers within the slave stations are disabled, but they continuously monitor the data stream sent out from the master station. When the slave stations' receivers detect an address character, each receiver notifies its respective CPU by setting receiver ready (-RXRDY) and generating an interrupt, if programmed to do so. Each slave station CPU then compares the received address to its station address and enables its receiver if the addresses match. Slave stations that are not addressed, continue monitoring the data stream for the next address character. An address character marks the beginning of a new block of data. After receiving a block of data, the slave stations CPU may disable the channel receiver and re-initiate the process. A transmitted character from the master station consists of a start bit, the programmed number of data bits, an address/data (A/D) bit tag (replacing the parity bit used in normal operation), and the programmed number of stop bits. The A/D tag indicates to the slave stations channel whether the character should be interpreted as an address character or a data character. The character is interpreted as an address character if the A/D tag is set to a '1' or interpreted as a data character if it is set to a '0'. The polarity of the transmitted A/D tag is selected by programming MR1A, MR1B bit-2 to a '1' for an address character and to a '0' for data characters. Users should program the mode register prior to loading the corresponding data or address characters into the transmit buffer. As a slave station, the XR68C92/192 receiver continuously monitors the received data stream regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the receiver ready status bit and loads the character into the FIFO receive holding register stack provided the received A/D tag is a '1' (address Rev. 1.33
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tag). The received character is discarded if the received address/data bit is a '0' (data tag). If the receiver is enabled, all received characters are transferred to the CPU during read operations. In either case, the data bits are loaded into the data portion of the FIFO stack while the address/data bit is loaded into the status portion of the FIFO stack normally used for parity error (SRA, SRB bit-5). Framing error, overrun error, and break-detection operate normally regardless of whether the receiver is enabled or disabled. The address/data (A/D) tag takes the place of the parity bit and parity is neither calculated nor checked for characters in this mode. Extra Storage For The A/D Tag: The unique feature of XR68C92/192 is that the the user need not wait at all in order to change the A/D tag from address to data (whereas in the case of SC26C92, a wait of at least 2 bit-times is required before changing the A/D tag). This allows the user to possibly load the entire polling packet data to the TX FIFO. WATCHDOG TIMER Each of the two receivers (channel A & B) has its own 'watchdog timer' which is separate from and independent of the Counter/Timer. The watchdog timer is used to generate a receive ready time-out interrupt. When it is enabled, a counter is started everytime a character is transferred from the receive shift register to the receive FIFO and times out after 64 bit-times, at which point it will generate a receive interrupt. This is a useful feature especially when the incoming data is not a continous stream of data. For example, if RX trigger levels are used and the last set of characters is smaller than the trigger level, a receive time-out interrupt is generated instead of a regular receive interrupt. The watchdog timer, however, is not accurate as it uses the incoming data for its timing. For more accurate timing, the time-out mode in Counter/Timer should be used (see below). COUNTER/TIMER The 16-bit counter/timer (C/T) can operate in a counter mode or a timer mode. In either mode, users can program the C/T input clock source to come from several sources (see ACR bits 6:4) and program the C/T output to appear on output port pin OP3 (see OPCR bits 3:2). The value (pre-load value) stored in the concatenation of the C/T upper register (CTPU, address 0x6) and the C/T lower register (CTPL, ad-
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dress 0x7) can be from 0x0001 through 0xFFFF and can be changed at any time. At power-up and after reset, the C/T operates in counter mode. COUNTER MODE In counter mode, the CPU can start and stop the C/T. This mode allows the C/T to function as a system stopwatch or a real-time single interrupt generator. In this mode, the C/T counts down from the pre-load value using the programmed counter clock source. When a read at the start counter command register (address 0xE) is performed, the counter is initialized to the pre-load value and begins a countdown sequence. When the counter counts from 0x0001 to 0x0000 (terminal count), the C/T-ready bit in the interrupt status register (ISR Bit-3) is set. 3 Users can program the counter to generate an interrupt request for this condition on the -INT output by unmasking the bit-3 in the Interrupt Mask Register (IMR, address 0x5). After 0x0000 the count becomes 0xFFFF, and the counter continues counting down from there. If the CPU changes the pre-load value, the counter will not recognize the new value until it receives the next start counter command (and is reinitialized). When a read at the stop counter command register (address 0xF) is performed, the counter stops the countdown sequence and clears ISR Bit-3. The count value should only be read while the counter is stopped because only one of the count registers (either CUR, at address 0x6 or CLR, at address 0x7) can be read at a time. If the counter is running, a decrement of CLR that requires a borrow from the CUR could take place between the two register reads. Figure 2 shows the C/T output in the counter mode. OP3 can be programmed to show the C/T output. In addition to the watch dog timer described above, the C/T can be used for receive timeout function (see description under CRA, CRB in the registers section also). The C/T is more accurate and the timeout period is programmable unlike the watchdog timer. However, only one channel can use the C/T for receive timeout at any given time. The C/T timeout mode uses the received data stream to start the counter. Each time a character is shifted from the receive shift register to the receive FIFO, the C/T is reloaded with the programmed value in CTPU and CTPL and it restarts on the next C/T clock. If a new character is not received before the C/T reaches terminal count (= 0x0000), a counter ready interrupt (ISR bit-3) is generated. The user can appropriately program the CTPU and CTPL for the desired timeout period. Typically this is slightly more than one character time. Note that if C/T is used for receiver timeout, a counter ready interrupt is generated whereas if the watchdog timer is used, a receiver ready interrupt is generated. TIMER MODE In the timer mode, the C/T runs continuously once the start command is issued (by reading the start C/T
START C/T COMMAND ISSUED
PRELOAD TERMINAL PRELOAD TERMINAL PRELOAD TERMINAL VALUE COUNT VALUE COUNT VALUE COUNT C/T OUTPUT IN TIMER MODE PRELOAD TERMINAL VALUE COUNT PRELOAD TERMINAL VALUE COUNT C/T OUTPUT IN COUNTER MODE PRELOAD TERMINAL COUNT VALUE
PRELOAD VALUE
PRELOAD TERMINAL VALUE COUNT
Figure 2: C/T output in Timer and Counter modes.
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command register) and the CPU cannot stop it. When the stop command is issued (by reading the stop C/T command register), the CPU only resets the C/T interrupt. This mode allows the C/T to be used as a programmable clock source for channels A and B (see CSRA, CSRB register), and/or a periodic interrupt generator. In this mode, the C/T generates a squarewave output (see Figure 2) derived from the programmed timer input clock source. The square wave generated by the timer has a period of 2 X (pre-load value) X (period of clock source) and is available as a clock source for both channels A and B. Since the timer cannot be stopped, the values in the registers (CUR:CLR) should not be read. See description of ACR register to see how to choose clock source for the C/T. When the start counter command register (STCR, address 0xE) is read, the C/T terminates the current countdown sequence and sets its output to a '1' (OP3 can be programmed to show this output). The C/T is then initialized to the pre-load value, and begins a new countdown sequence. When the terminal count is reached (0x0000), the C/T sets its output to a '0'. Then, it gets re-initialized to the pre-load value and repeats the countdown sequence. See Figure 2 for the resulting waveform. The timer sets the C/T-ready bit in the interrupt status register (ISR Bit-3) every other time it reaches the terminal count (at every rising edge of the output). Users can program the timer to generate an interrupt request for this condition (every second countdown cycle) on the -INT output. If the CPU changes the preload value, the timer will not recognize the new value until either (a) it reaches the next terminal count and is reinitialized automatically, or (b) it is forced to re-initialize by a start command. When a read at the stop counter command address is performed, the timer clears ISR Bit-3 but does not stop. Because in timer mode the C/T runs continuously, it should be completely configured (pre-load value loaded and start counter command issued) before programming the timer output to appear on OP3. OTHER PROGRAMMING REMARKS The contents of internal registers should not be changed during receiver/transmitter operation as certain changes can produce undesired results. For example, changing the number of bits per character while the transmitter is active will result in transmitting an incorrect character. The contents of the clock-select register (CSR) and ACR Bit-7 should only be changed after the receiver(s) and transmitter(s) have been issued software RX and TX reset commands. Similarly, changes to the auxiliary control register (ACR Bits 4-6) should only be made while the counter/timer (C/T) is not used. The mode registers of each channel MR0, MR1 and MR2 are accessed via an auxiliary pointer. The pointer is set to mode register one (MR1) by RESET. It can be set to MR0 or MR1 by issuing a "reset pointer" command (0xB0 or 0x10 respectively) via the channel's command register. Any read or write of the mode register switches the pointer to next mode register. All accesses subsequent to reading/writing MR1 will address MR2 unless the pointer is reset to MR0 or MR1 as described above. The mode, command, clock-select, and status registers are duplicated for each channel to allow independent operation and control (except that both channels are restricted to baud rates that are in the same set).
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INTERNAL REGISTER DESCRIPTIONS A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 READ Operation Mode Register A (MR0A, MR1A, MR2A) Status Register A (SRA) Reserved Receiver Buffer A (RXA) Input Port Change Register (IPCR) Interrupt Status Register (ISR) Counter/Timer Upper Register (CUR) Counter/Timer Lower Register (CLR) Mode Register B (MR0B, MR1B, MR2B) Status Register B (SRB) Reserved Receiver Buffer B (RXB) Interrupt Vector Register (IVR) Input Port Register (IPR) Start C/T Command (STCR) Stop C/T Command (SPCR) WRITE Operation Mode Register A (MR0A, MR1A, MR2A) Clock-Select Register A (CSRA) Command Register A (CRA) Transmitter Buffer A (TXA) Auxiliary Control Register (ACR) Interrupt Mask Register (IMR) C/T Preload value Upper Register (CTPU) C/T Preload value Lower Register (CTPL) Mode Register B (MR0B, MR1B, MR2B) Clock-Select Register B (CSRB) Command Register B (CRB) Transmitter Buffer B (TXB) Interrupt Vector Register (IVR) Output Port Configuration Register (OPCR) Set Output Port Register (SOPR) Reset Output Port Register (ROPR)
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A3 A2 A1 A0 0 0 0 0 Register [Default] MRA0[00] BIT-7 Watch dog timer Watch dog timer BIT-6 RX trigger level [1] RX trigger level [1] RX trigger level [0] BIT-5 TX trigger level [1] TX trigger level [1] Error mode TX RTS control Parity error RX clock Misc. command Bit-5 Bit-5 Delta IP1 C/T mode RxB ready RxB ready Bit-13 BIT-4 TX trigger level [0] TX trigger level [0] Parity mode Auto CTS control Overrun error RX clock Misc. command Bit-4 Bit-4 Delta IP0 C/T mode TxB ready TxB ready Bit-12 BIT-3 Not used Not used BIT-2 Baud rate ext. 2 Not used BIT-1 Factory test mode Not used BIT-0 Baud rate ext. 1 Not used
1
0
0
0
MRB0[00]
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0
0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0
MRA1[00] MRB1[00] MRA2[00] MRB2[00] SRA[00] SRB[00] CSRA[00] CSRB[00] CRA[00] CRB[00] RXA[XX] RXB[XX] TXA[XX] TXB[XX] IPCR[00] ACR[00]
RX RTS control
Parity mode Stop bit length Tx empty TX clock TX disable Bit-3 Bit-3 IP3 input Delta IP3 int. C/T ready C/T ready Bit-11
Parity type Stop bit length Tx ready TX clock TX enable Bit-2 Bit-2 IP2 input Delta IP2 int. Delta break A Delta break A Bit-10
Word length Stop bit length Rx FIFO full TX clock RX disable Bit-1 Bit-1 IP1 input Delta IP1 int. RxA ready RxA ready Bit-9
Word length Stop bit length Rx ready TX clock RX enable Bit-0 Bit-0 IP0 input Delta IP0 int. TxA ready TxA ready Bit-8
Loopback Loopback mode mode select select Received break RX clock Misc. command Bit-7 Bit-7 Delta IP3 Baud rate set select Input port change Input port change Bit-15 Framing error RX clock Misc. command Bit-6 Bit-6 Delta IP2 C/T mode Delta break B Delta break B Bit-14
0
1
0
1
ISR[00]
0
1
0
1
IMR[00]
0
1
1
0
CTPU[00] CUR[00]
0
1
1
1
CTPL[00] CLR[00]
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 1 1 1 1
1 1 1 1 1 1 1
0 0 0 1 1 1 1
0 1 1 0 0 1 1
IVR[0F] IPR[XX] OPCR[00] STCR[XX] SOPR[00] SPCR[XX] ROPR[00]
Bit-7 Not Used OP7 X Bit-7 X Bit-7
Bit-6 Not Used OP6 X Bit-6 X Bit-6
Bit-5 IP5 OP5 X Bit-5 X Bit-5
Bit-4 IP4 OP4 X Bit-4 X Bit-4
Bit-3 IP3 OP3 X Bit-3 X Bit-3
Bit-2 IP2 OP3 X Bit-2 X Bit-2
Bit-1 IP1 OP2 X Bit-1 X Bit-1
Bit-0 IP0 OP2 X Bit-0 X Bit-0
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MODE REGISTER 0 (MR0A, MR0B) This register is accessed only when command is applied via CRA, CRB register (upper nibble = 0xB). After reading or writing to MR0A (or MR0B) register, the mode register pointer will point to MR1A (or MR1B) register. MR0A Bit-0: Extended baud rate table selection for both channels. 0 = Normal baud rate tables 1 = Extended baud rate tables 1 MR0A Bit-1: Special Function. 0 = Normal 1 = Factory test mode MR0A Bit-2: Extended baud rate table selection for both channels. 0 = Normal baud rate tables 1 = Extend baud rate tables 2 MR0A Bit-3, MR0B Bits 3-0: Not Used. Any write to this bit is ignored. MR0A, MR0B Bits 5-4: Transmit trigger level select. Bit-5 0 0 1 1 Bit-5 0 0 1 1 Bit-4 0 1 0 1 Bit-4 0 1 0 1 8 4 6 1 16 6 12 1 XR68C92 FIFO locations empty (default) FIFO locations empty FIFO locations empty FIFO location empty XR68C192 FIFO locations empty (default) FIFO locations empty FIFO locations empty FIFO location empty MR0A, MR0B Bit-7: Receive time-out (watch dog timer). 0 = Disabled (default) 1 = Enabled See description under 'Watchdog Timer'. MODE REGISTER 1 (MR1A, MR1B) MR1A, MR1B are accessed after reset or by command applied via CRA, CRB register (upper nibble = 0x1). After reading or writing to MR1A (or MR1B) register, the mode register pointer will point to MR2A (or MR2B) register. MR1A, MR1B Bits 1-0: Character Length 0 0 = 5 (default) 10=7 01=6 11=8 MR1A, MR1B Bit-2: In non-Multidrop mode, this bit selects the parity. 0 = Even Parity (default) 1 = Odd Parity In Multidrop mode, this bit is the Address/Data flag. 0 = Data (default) 1 = Address MR1A, MR1B Bit 4-3: Parity mode. 00 = With parity (default) 10 = No parity 01 = Force parity 11 = Multidrop mode MR1A, MR1B Bit-5: Data error mode. 0 = Single Character mode (default) 1 = Block (FIFO) mode MR1A, MR1B Bit-6. Receive trigger levels. See description under MR0 bit6. MR1A, MR1B Bit-7: Receive RTS flow control. 0 = No RX RTS control function (default) 1 = Auto RX RTS control function The output OP0 (OP1) serves as the -RTS signal for channel A (channel B). Note that MR2 A/B bit-5 also controls OP0 (OP1). Only one of MR1 bit-7 or MR2 bit5 should be set to '1'. MODE REGISTER 2 (MR2A, MR2B) This register is accessed after any read or write operation to MR1A (or MR1B) register is performed. Any read or write to MR2A (or MR2B) does not change the mode register pointer. User should use one of the
MR0A, MR0B Bit-6: Receive trigger level select. This bit is associated with MR1 Bit-6. MR0 Bit-6 0 0 1 1 MR0 Bit-6 0 0 1 1 MR1 Bit-6 0 1 0 1 MR1 Bit-6 0 1 0 1 1 3 6 8 XR68C92 byte in FIFO (default) bytes in FIFO bytes in FIFO bytes in FIFO XR68C192 byte in FIFO (default) bytes in FIFO bytes in FIFO bytes in FIFO
1 6 12 16
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two reset MR pointer command (see Command Register) to reset the pointer to MR0 or MR1. MR2A, MR2B Bits 3-0: Stop bit length. 0000 = 0.563 (default) 1000 = 1.563 0001 = 0.625 1001 = 1.625 0010 = 0.688 1010 = 1.688 0011 = 0.750 1011 = 1.750 0100 = 0.813 1100 = 1.813 0101 = 0.875 1101 = 1.875 0110 = 0.938 1110 = 1.938 0111 = 1.000 1111 = 2.000 MR2A, MR2B Bit-4: Auto CTS Flow control. 0 = No Auto CTS flow control (default) 1 = Auto CTS flow control enabled MR2A, MR2B Bit-5: Auto Transmit RTS control. 0 = No Auto TX RTS control (default) 1 = Auto Transmit RTS function enabled The output OP0 (OP1) serves as the -RTS signal for channel A (channel B). Note that only one of MR1 bit7 or MR2 bit-5 should be set to '1'. MR2A, MR2B Bit 7-6: Loopback mode select. 0 0 = No loopback (default) 0 1 = Automatic Echo 1 0 = Local Loopback 1 1 = Remote Loopback STATUS REGISTER (SRA, SRB) SRA, SRB Bit-0: Receive Ready. This bit indicates that one or more character(s) has been received and is waiting in the FIFO for the CPU to read them. It is set when the first character is transferred from the receive shift register to the empty FIFO, and cleared when the CPU reads the receiver buffer and there are no more characters in the FIFO after the read. SRA, SRB Bit-1: Receive FIFO Full. This bit is set when a character is transferred from the receive shift register to the receiver FIFO and the transfer fills the FIFO. All eight (or 16 in XR88C192) FIFO locations are occupied. It is cleared when the CPU reads the receiver buffer, unless another character is in the receive shift register waiting for an empty FIFO location. SRA, SRB Bit-2: Transmit Ready. This bit (when set) indicates that the transmit FIFO is not full. Transmitter ready bit is set when the transmit FIFO has at least one empty location. This bit is cleared when the transmit FIFO is full. Rev. 1.33
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SRA, SRB Bit-3: Transmit Empty. This bit will be set when the channel's transmitter is empty. It indicates that both the transmit FIFO and the transmit shift register are empty. It is set after transmission of the last stop bit of the last character in the TX FIFO. It is cleared when the CPU loads a character into the transmit FIFO or when the transmitter is disabled. SRA, SRB Bit-4: Overrun Error. This bit is set when one or more characters in the received data stream have been lost. It is set on receipt of a valid start bit when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error, and framing error status, if any) is overwritten. A reset error status command clears this bit. SRA, SRB Bit-5: Parity Error. This bit is set when the "with parity" or "force parity" mode is programmed by MR1A (or MR1B) and an incoming character is received with incorrect parity. In the Multidrop mode, the parity error bit position stores the received address/data tag. This bit is valid only when the RxRDY bit is set (SRA, SRB bit-0 = 1). SRA, SRB Bit-6: Framing Error. This bit is set when a stop bit was not detected when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position. At least one bit in the received character (data or parity) must have been a "1" to signal a framing error. After a framing error, the receiver does not wait for the line to return to the marking state (high). If the line remains low for 1/2 a bit time after the stop bit sample (that is, the nominal end of the first stop bit), the receiver treats it as the beginning of a new start bit.This bit is valid only when the RxRDY bit is set (SRA, SRB Bit-0 = 1). SRA, SRB Bit-7: Received Break. This bit indicates a character with all data bits being zero has been received without a stop bit. This bit is valid only when the RxRDY bit is set (SRA, SRB Bit-0 = 1). Only a single FIFO position is occupied when a break is received; for longer break signals, additional entries to the FIFO are inhibited until the channel A/B receiver serial data input line returns to the marking state. The break-detect circuitry can detect a break that starts in the middle of a received character however, the break condition must persist completely through the end of the current character and the next character time to be recognized as a break signal.
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Baud Rate Table for a 3.6864MHz clock. Data rates would double for a 7.3728MHz clock. MR0A Bits 2,0=0 CSRA, CSRB Bits 7:4 or Bits 3:0 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110* 1111* SET-1 ACR Bit-7=0 50 110 134.5 200 300 600 1200 1050 2400 4800 7200 9600 38.4k Timer SET-2 ACR Bit-7=1 75 110 134.5 150 300 600 1200 2000 2400 4800 1800 9600 19.2k Timer MR0A Bit-0=1 Bit-2=0 (extended table 1) SET-1 ACR Bit-7=0 300 110 134.5 1200 1800 3600 7200 1050 14.4k 28.8k 7200 57.6k 230.4k Timer SET-2 ACR Bit-7=1 450 110 134.5 900 1800 3600 7200 2000 14.4k 28.8k 1800 57.6k 115.2k Timer MR0A Bit-0=0 Bit-2=1 (extended table 2) SET-1 ACR Bit-7=0 4800 880 1076 19.2k 28.8k 57.6k 115.2k 1050 57.6k 4800 57.6k 9600 38.4k Timer SET-2 ACR Bit-7=1 7200 880 1076 14.4k 28.8k 57.6k 115.2k 2000 57.6k 4800 14.4k 9600 19.2k Timer
IP3-16X (CSRA 3:0), IP4-16X (CSRA 7:4), IP5-16X (CSRB 3:0), IP6-16X (CSRB 7:4) IP3-1X (CSRA 3:0), IP4-1X (CSRA 7:4), IP5-1X (CSRB 3:0), IP6-1X (CSRB 7:4)
* Baud Rate is independent of MR0 bit-0 & bit-2 and ACR bit-7 settings. CLOCK SELECT REGISTER (CSRA, CSRB) Transmit / Receive baud rates for channels A, B can be selected via this register. CSRA, CSRB Bits 3-0. Transmit clock select(see baud rate table). CSRA, CSRB Bits 7-4. Receive clock select (see baud rate table). COMMAND REGISTER (CRA, CRB) CRA, CRB register is used to supply commands to A, B channels respectively. Multiple commands can be specified in a single write to CRA, CRB as long as commands are non-conflicting. CRA, CRB Bits 1-0: Receiver Commands. 0 0 = No Action, Stays in Present Mode (default) 0 1 = Receiver Enabled 1 0 = Receiver Disabled 1 1 = Don't Use Rev. 1.33
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CRA, CRB Bits 3-2: Transmitter Commands. 0 0 = No Action, Stays in Present Mode (default) 0 1 = Transmitter Enabled 1 0 = Transmitter Disabled 1 1 = Don't Use CRA, CRB Bits 7-4: Miscellaneous Commands. 0 0 0 0 = No Command (default). 0 0 0 1 = Reset MR Pointer to MR1. 0 0 1 0 = Reset Receiver. Receiver is disabled and FIFO is flushed. 0 0 1 1 = Reset Transmitter. Transmitter is disabled and FIFO is flushed. 0 1 0 0 = Reset Error Status. Clears channel A/B, break, parity, and over-run error bits in the status register. 0 1 0 1 = Reset Channel's Break-Change Interrupt. Clears channel A/B break detect change bit in the interrupt status register (ISR bit-2 for channel A and ISR bit-6 for channel B).
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0 1 1 0 = Start Break. Forces the transmitter output to go low and stay low. If transmitter is empty the start of the break condition will be delayed up to two bit times. If transmitter is active, all the characters in the FIFO are transmitted before break signal is sent. Transmitter must to be enabled for this command to work. 0 1 1 1 = Stop Break. Transmit output will go high within two bit times. 1 0 0 0 = Set -RTS output to low (assertion). 1 0 0 1 = Reset -RTS output to high (negation). 1 01 0 = Set Timeout Mode On. The receiver in this channel will restart the C/T as each receive character is transferred from the shift register to the receive FIFO. The C/T is placed in the counter mode, the START/STOP counter commands are disabled, the counter is stopped, and the Counter Ready Bit, ISR Bit-3 is reset. (See also Watchdog timer description) 1 0 1 1 = Set MR pointer to MR0. 1 1 0 0 = Disable Timeout Mode. This command returns control of the C/T to the regular Start/ Stop counter commands. It does not stop the counter or clear any pending interrupts. After disabling the timeout mode, a "Stop Counter" command should be issued to force a reset of the ISR Bit-3. 1 1 0 1 = Not used. 1 1 1 0 = Enable Power Down Mode. In this mode, the DUART oscillator is stopped and all functions requiring this clock are suspended. The execution of commands other than disable power down mode (1111) requires a XTAL1. While in the power down mode, do not issue any commands to the CRA or CRB except the disable power down mode command. The contents of all registers will be saved while in this mode. It is recommended that the transmitter and receiver be disabled prior to placing the DUART into power down mode. This command is in CRA only. 1 1 1 1 = Disable Power Down Mode. This command restarts the oscillator. After invoking this command, wait for the oscillator to start up before writing further commands to the CR A/ B. For maximum power reduction all input pins should be at GND or VCC. This command is in CRA only. Rev. 1.33
20
RECEIVE BUFFER (RXA, RXB) The receive buffer consists of a 8-characters deep FIFO in XR68C92 and 16-characters deep FIFO in XR68C192. The received characters are transferred from the shift register one at a time to the FIFO and are stored there until read by the CPU or flushed by a reset receiver command. TRANSMIT BUFFER (TXA, TXB) The transmit buffer consists of a 8-characters deep FIFO in XR68C92 and 16-characters deep FIFO in XR68C192. Once loaded in the FIFO, the characters are transferred to the transmit shift register one at a time and transmitted unless the transmitter is disabled. INPUT PORT CHANGE REGISTER (IPCR) This is a read-only register which gives the state and the change-of-state information of the multi-purpose inputs IP0, IP1, IP2 and IP3. IPCR Bits 3-0: Levels of IP3 - IP0. These show the current state of IP3, IP2, IP1 and IP0 respectively. 0 = Low 1 = High IPCR Bits 7-4: Transitions of IP3 - IP0. These indicate if there has been a change of state in IP3, IP2, IP1 and IP0 respectively. They are cleared when the register is read by the CPU. 0 = No 1 = Yes AUXILIARY CONTROL REGISTER (ACR) ACR Bits 3-0: This field selects which bits of the input port change register (IPCR) cause the interrupt status register (ISR) bit-7 to be set. For example, if bit-0 = 1, then a change of state in IP0 will set ISR bit-7. If bit-0 and bit2 are both '1', then whenever IP0 or IP2 changes state, ISR bit-7 will be set. 0 = Disabled (default) 1 = Enabled ACR Bits 6-4: Counter/Timer Mode and Clock Source. These bits should not be altered while the C/T is in use. Prior to changing these bits, the C/T must be stopped if in counter mode. If the C/T is in timer mode, its output
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must be disabled and its interrupt must be masked. The following table shows how to select the clock source for the C/T when used in counter mode or timer mode: ACR Bit-7: Baud rate table Select. This bit is used to select between two sets of baud rate tables. See Baudrate table on Page 18. It should be changed only after both channels have been reset and disabled. 0 = Set 1 1 = Set 2 ACR Bits 6:4 000 001 010 011 100 101 110 111 C/T Mode Counter Counter Counter Counter Timer Timer Timer Timer Clock Source External (IP2) TXAClk1-Transmit A 1X clock TXBClk1-Transmit B 1X clock Crystal or External Clock (XTAL1/Clk) Divided by 16 External (IP2) External (IP2) Divided by 16 Crystal or External Clock (XTAL1/Clk) Crystal or External Clock (XTAL1/Clk) Divided by 16 ISR Bit-1: Receive ready A . This bit is set when channel A's receive buffer (FIFO) is filled above the programmed receive trigger level condition (see MR0A bit-6 and MR1A bit-6). For example, if a RX trigger level of '6' is chosen, this bit will be set whenever the RX FIFO contains six or more bytes. This bit can be cleared by reading the data out of the FIFO till it falls below the trigger level. ISR Bit-2: Channel A change in break. This bit is set when channel A receiver detects the beginning or the end of a break condition. It is reset when the CPU issues a channel A reset break change interrupt command (CRA bits 7-4 = 0x5). ISR Bit-3: Counter/Timer (C/T) ready. In counter mode, this bit is set when the C/T reaches terminal count. In timer mode, this bit is set each time the C/T output switches from low to high (rising edge see Figure 2). In either mode, this bit is cleared by a stop counter command. ISR Bit-4: Transmit ready B. This bit is set when channel B's transmit buffer (FIFO) is filled below the programmed transmit trigger level (see MR0B bits 5-4). For example, if a TX trigger level of '4' is chosen, this bit will be set whenever the TX FIFO has four or more empty locations. This bit can be cleared by loading the TX FIFO above the trigger level. ISR Bit-5: Receive ready B. This bit is set when channel B's receive buffer (FIFO) is filled above the programmed receive trigger level condition (see MR0B bit-6 and MR1B bit-6). For example, if a RX trigger level of '6' is chosen, this bit will be set whenever the RX FIFO contains six or more bytes. This bit can be cleared by reading the data out of the FIFO till it falls below the trigger level. ISR Bit-6. Channel B change in break. This bit is set when channel B receiver detects the beginning or the end of a break condition. It is reset when the CPU issues a channel B reset break change interrupt command (CRB bits 7-4 = 0x5). ISR Bit-7. Input port change status. This bit is set when a change of state has occurred at the IP0, IP1, IP2, or IP3 inputs, and that event has been enabled to cause an interrupt by programming ACR Bits 3-0. This bit is cleared when the CPU reads the input port change register.
INTERRUPT STATUS REGISTER (ISR) This register provides the status of all potential interrupt sources. The contents of this register are logically "AND"-ed with the contents of the interrupt mask register, and the results are "OR"-ed. The resulting signal is inverted to produce the -INT output. All active interrupt sources are visible by reading the ISR, regardless of the contents of the interrupt mask register. Reading the ISR has no effect on any interrupt source. Each active interrupt source must be cleared in a source-specific fashion to clear the ISR. All interrupt sources are cleared when the XR68C92/192 is reset.4 ISR Bit-0: Transmit ready A. This bit is set when channel A's transmit buffer (FIFO) is filled below the programmed transmit trigger level (see MR0A bits 5-4). For example, if a TX trigger level of '4' is chosen, this bit will be set whenever the TX FIFO has four or more empty locations. This bit can be cleared by loading the TX FIFO above the trigger level.
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INTERRUPT MASK REGISTER (IMR) This register selects which bits in the interrupt status register can cause an interrupt output. If a bit in the interrupt status register is a "1" and the corresponding bit in this register is also a "1", the -INT output will be asserted. If the corresponding bit in this register is a zero, the state of the bit in the interrupt status register has no effect on the -INT output. Note that the interrupt mask register does not have any effect on the programmable interrupt outputs OP7 through OP3 or the value read from the interrupt status register. 0 = Interrupt output (-INT) disabled (default) 1 = Enable interrupt output for the event controlled by the corresponding bit in ISR. COUNTER / TIMER REGISTERS The Preload value Upper (CTPU) and Lower (CTPL) registers hold the most-significant byte and the leastsignificant byte, respectively, of the value to be used by the C/T (in both counter and timer modes). The C/T Upper (CUR) and Lower Registers (CLR) give the current value of the C/T, at the time they are read. In the counter mode, the CUR and CLR should only be read when the counter is stopped. Upon receiving a start command after a stop command, the counter starts a fresh cycle and begins counting down from the original (preload) value written to CTPU and CTPL. Also changing the value of these registers does not take effect till the current cycle is stopped and a subsequent start command is issued. In the timer mode, the CUR and CLR registers cannot be read by the CPU. A stop command will not stop the timer, but will only clear the counter ready status bit in ISR (bit-3). Changing the value of the CTPU and CTPL registers when the timer is running will change the waveform after the current half-period of the square wave. For more details, see the Counter/Timer section. GENERAL PURPOSE REGISTER (GPR) This is a general purpose scratchpad register which can be used to store and retrieve one byte of user infomation. INPUT PORT REGISTER - Read Only The current state of the multi-purpose inputs (IP0-IP6) can be read via this register. IPR Bit 0-5: 0 = Inputs are in low state. 1 = Inputs are in high state. IPR Bit 6-7: Not used and set to "0". OUTPUT PORT CONFIGURATION REGISTER (OPCR) - Write Only This register selects following options for the multipurpose outputs OP2 to OP7.4Alternate functions of OP1 and OP0 are controlled by the mode registers, not the OPCR. MR1A Bit-7 and MR2A Bit-5 control OP0. MR1B Bit-7 and MR2B Bit-5 control OP1. For more details on these, see 'Multi-purpose Outputs' on page 8. OP2 Output Select Bit-1 Bit-0 0 0 Controlled by SOPR and ROPR (default) 0 1 TxAClk16-Transmit A 16X clock 1 0 TxAClk1-Transmit A 1X clock 1 1 RxAClk1- Receive A 1X clock OP3 Output Select Bit-3 Bit-2 0 0 Controlled by SOPR and ROPR (default) 0 1 C/T Output 1 0 TxBClk1-Transmit B 1X clock 1 1 RxBClk1- Receive B 1X clock If OP3 is to be used for the timer output (a square wave of the programmed frequency), program the counter/ timer for timer mode (ACR Bit-6 = 1), initialize the counter/timer pre-load registers (CTPU and CTPL), and read the 'Start C/T Command Register' (STCR) before setting OPCR Bits 3-2 = 01. In the counter mode, the output remains high until the terminal count is reached, at which time it goes low. The output becomes high again when the counter is stopped by a stop counter command. OP4 output select (Bit 4): 0 = Controlled by SOPR and ROPR (default) 1 = -RxARDY which is the complement of ISR bit-1
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OP5 output select (Bit 5): 0 = Controlled by SOPR and ROPR (default) 1 = -RxBRDY which is the complement of ISR bit-5 OP6 output select (Bit 6): 0 = Controlled by SOPR and ROPR (default) 1 = -TxARDY which is the complement of ISR bit-0 OP7 output select (Bit 7): 0 = Controlled by SOPR and ROPR (default) 1 = -TxBRDY which is the complement of ISR bit-4 START COUNTER/TIMER REGISTER (STCR) Read Only RESET OUTPUT PORT REGISTER (ROPR) - Write Only Each output port bit can be changed to high state by writing a "1" to each individual bit. ROPR Bit 0-7: 0 = No change (same state). 1 = Negate the corresponding output (Set it high).
Reading from this register will start the C/T. Data values returned should be ignored. STOP COUNTER/TIMER REGISTER (SPCR) Read Only Reading from this register will stop the C/T. Data values returned should be ignored. SET OUTPUT Write Only PORT REGISTER (SOPR) -
Output ports (OP0-OP7), when used as general purpose outputs, can be asserted (set to low) by writing a "1" to the corresponding bit in this register. Once an output is asserted, it can be negated only by issuing a command through the Reset Output Port Register (see below). However, note that SOPR and ROPR cannot be used to assert and negate outputs that are programmed for alternate functions (see description under OPCR). For example, if OP0 is programmed to output -RTSA (see 'Configuring Multi-purpose Outputs), it cannot be controlled by SOPR or ROPR. In that case, commands from the Command Register should be issued to assert (CRA bits 7:4 = 0x8) and negate (CRA bits 7:4 = 0x9) OP0. SOPR Bit 0-7: 0 = No change (same state). 1 = Assert the corresponding output (Set it low).
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PROGRAMMING EXAMPLES The following examples show how to initialize the XR68C92/192 for various operating conditions: A) The first example will initialize channel A of an XR68C92 device for regular RX/TX. The operating parameters will be 9600 baud, 8 word length, no parity and 1 stop bit. Operation
Write Write Write Write Write Write Write Write Write Read
Register
CRA CRA CRA CRA MR0A MR1A MR2A CSRA CRA SRA
Value
0x20 0x30 0x40 0xB0 0x00 0x13 0x07 0xBB 0x05
Remarks
; reset RX (receiver) ; reset TX (transmitter) ; reset error status ; reset MR pointer to MR0 ; use normal baud rate table. Now MR pointer points to MR1 ; select word length & parity. Now MR pointer points to MR2 ; normal mode (not loopback) & 1 stop bit ; 9600 baud for RX & TX - clock source is XTAL1 ; enable RX & TX ; should get a value 0x0C
B) This example will show how to use hardware flow control for both RX (RTS via OP0) and TX (CTS via IP0):
Write Write Write CRA MR1A MR2A 0x10 0x93 0x17 ; reset MR pointer to MR1 ; select auto RTS control. The -RTS signal is sent via output OP0 ; select auto CTS control. The input IP0 serves as the -CTS signal
C) This example will configure clock sources for TX and RX of both channels and C/T. Specifically, XTAL1 will be used as channel A's TX clock; IP4 as channel A's 16X RX clock; IP5 as channel B's 1X TX clock and XTAL1 as channel B's RX clock. Also, the C/T will be initialized in the timer mode and IP2 will be used as its clock source. Some of these will be programmed to appear at the multi-purpose output pins:
Write Write Write Write Write Read Write ACR CTPU CTPL CSRA CSRB STCR OPCR ; C/T initialized in timer mode & IP2 chosen as its clock source ; also, bit-7 = 0, therefore baud rate Set1 has been selected 0x00 ; It is essential to program CTPU & CTPL before programming OP3 0x05 ; as C/T output (see below) 0xEB ; channel A RX clock source: IP4-16X, TX clock source: XTAL1 (if MR0A ; bits 2 and 0 = 0, the TX baud rate is 9600) 0xBF ; channel B RX clock source: XTAL1 (9600 baud), TX clock source: IP5-1X ; Start the C/T 0x06 ; C/T output appears at OP3 and channel A's TX 1X clock (this is XTAL1 ; clock divided by 16) at OP2. 0x40
D) The next example will show how to configure and run channel B's transmitter in a multi-drop application. Note that all other relevant parameters should be configured already, like baud rate etc.
Write Write Write Write Write Write Write Read CRB MR1B CRB TXB CRB MR1B TXB SRB 0x10 0x1B 0x04 address 0x10 0x13 data ; reset MR pointer to MR1 ; word length = 8 and use A/D tag in the place of parity ; Enable transmitter of channel B ; Send the address first (A/D tag = 1) ; reset MR pointer to MR1 ; change A/D tag = 0 ; You can load the data (A/D tag = 0) immediately after the address. There is no ; need to wait till the transmitter is empty. Load all the data. Check to see if the ; transmitter is empty & ready. You need to do this before you can load the next ; address. Repeat the last 5 steps to load different addresses and their data.
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ABSOLUTE MAXIMUM RATINGS
Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 7 Volts GND - 0.3 V to VCC +0.3 V -40 C to +85 C -65 C to 150 C 500 mW
DC ELECTRICAL CHARACTERISTICS FOR XR68C92 AND XR68C192
TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=3.3 - 5.0 V 10% unless otherwise specified.
Symbol
Parameter
Limits 3.3 Min Max -0.3 2.4 2.4 0.6 VCC 5.5
Limits 5.0 Min Max -0.5 3.0 3.0 0.6 VCC 5.5
Units Conditions
VILCK VIHCK VIHCK VIL VIH VIH VOL VOL VOH VOH IIL ICL ICC IPD IPD CP
Clock input low level Clock input high level (Devices with top marking of "CC" and older) Clock input high level (Devices with top marking of "D2" and newer) Input low level Input high level (Devices with top marking of "CC" and older) Input high level (Devices with top marking of "D2" and newer) Output low level on all outputs Output low level on all outputs Output high level Output high level Input leakage Clock leakage Avg power supply current Avg power-down supply current (68C92) Avg power-down supply current (68C192) Input capacitance
V V V
-0.3 2.0 2.0
0.8 VCC 5.5
-0.5 2.2 2.2
0.8 VCC 5.5
V V V
0.4 0.4 2.4 2.4 10 10 1.0* 100* 200* 5 10 10 1.5* 150* 300* 5
V V V V A A mA A A pF
IOL= 8 mA IOL= 5 mA IOH= -8 mA IOH= -1 mA
*All inputs tied to VCC/GND.
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AC ELECTRICAL CHARACTERISTICS
TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=3.3 - 5.0 V 10% unless otherwise specified.
Symbol
Parameter
Limits 3.3 Min Max 17 8 0 0 0 0 51 20 1 30 100 100 70 45 70 0 0 110 100 2 1 216-1
Limits 5.0 Min Max 17 24 0 0 0 0 32 10 1 20 70 70 42 27 43 0 0 110 100 2 1 216-1
Units
Conditions
T1w,T2w T3w TAS TAH TRWS TRWH TDD TDS TDH TDF TCSL TCSH TAKL TAKH TAKT T9s T9h T10d T11d TR N
Clock pulse duration Oscillator/Clock frequency Address Valid to -CS Low -CS High to Address Invalid R/-W Setup Time to -CS Low R/-W Hold Time from -CS High -CS/-IACK Low to Data Valid (Read) Data Valid to -CS High (Write) -CS High to Data Invalid (Write) -CS/-IACK High to Data Hi-Z (Read) -CS Low Pulse Width -CS High Pulse Width -CS/-IACK Low to -DACK Low -CS/-IACK High to -DACK High -CS/-IACK High to -DACK Hi-Z Port input setup time Port input hold time Delay from R/-W to output Delay to reset interrupt from -CS Reset pulse width Baud rate divisor
ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns clks* N/A
* number of input clock (crystal or external clock) periods
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TAS
TAH
A4-A1
TRWS TRWH
R/-W
TCSL TDD TDF
-CS
TCSH
D7-D0
Valid Data
TAKT
-DACK
TAKL TAKH
Read Cycle Timing
TAS TAH
A4-A1
TRWS TRWH
R/-W
TCSL TDS
-CS
TCSH TDH TAKT
D7-D0
-DACK
TAKL TAKH
Write Cycle Timing
Figure 3: Bus Timing (Read/Write cycle)
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IP6-IP0
T9s T9h XR92-IP
-CS
Figure 4: Input Port Timing
-CS
T10d
OP7-OP0
Old Data
New Data XR92-OP
Figure 5: Output Port Timing
T1w
T2w XR92-CK T3w
ExCLK
Figure 6: External clock Timing
-INT
-IACK
TDD TDF
D7-D0
TAKL
Interrupt Vector
TAKH
-DACK
TAKT
Hi-Z
Figure 7: Interrupt Timing
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RX RX ENABLE -RxRDY
D1
D2
D8
D9
D10
D11
D12
D13
D12, D13 Will be lost due to RX disable
-FFULL -RxRDY/ -FFULL -CS (Read) OVERRUN ERROR -RTS
XR92-RX
Status Data (D1)
D11 Will be lost due to overrun
Status Data Status Data Status Data (D2) (D3) (D10) Reset by command
Figure 8: Receive Timing
TX TX ENABLE -TxRDY
D1
D2
D3
Break
D4
D5
-CS (Write) -CTS
-RTS
XR692-TX
Figure 9: Transmit Timing Rev. 1.33
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XR68C92/192
P ACKAGE OUTLINE DRAW ING
40 L EAD PLASTIC DUAL-IN-LINE (PDIP)
40
21
E1
1
20
D
A2 Seat ing Plane A L B e E B1 A1
C
eA eB
Note: T he c ontrol dimens ion is the inc h c olumn SY MBOL A A1 A2 B B1 C D E E1 e eA eB L
INCHES MIN 0.160 0.015 0.125 0.014 0.030 0.008 1.980 0.600 0.485 MA X 0.250 0.070 0.195 0.024 0.070 0.014 2.095 0.625 0.580
MILLIMETERS MIN 4.06 0.38 3.18 0.36 0.76 0.20 50.29 15.24 12.32 MA X 6.35 1.78 4.95 0.56 1.78 0.38 53.21 15.88 14.73
0.100 BSC 0.600 BSC 0.600 0.115 00 0.700 0.200 15 0
2.54 BSC 15.24 BSC 15.24 2.92 00 17.78 5.08 15 0
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P ACKAGE OUTLINE DRAW ING
44LEAD PLASTIC LEADED CHIP CARRIER (PL CC)
D D
1
C Seat ing Plane 45 x H 2 45 x H 1 A2
2
1
44
B1
D
D1
D3
B
D2
e
R D3 A1 A
Note: The c ontrol dimens ion is the inc h c olumn SY MBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R INCHES MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.685 0.650 0.590 MA X 0.180 0.120 ----0.021 0.032 0.013 0.695 0.656 0.630 MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 17.40 16.51 14.99 MA X 4.57 3.05 -----0.53 0.81 0.32 17.65 16.66 16.00
0.500 ty p 0.50 BSC 0.042 0.042 0.025 0.056 0.048 0.045
12.70 ty p 1.27BSC 1.07 1.07 0.64 1.42 1.22 1.14
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PACKAGE OUTLINE DRAWING
44 LEAD LOW-PROFILE QUAD FLAT PACK (LQFP)
D 3 3 D1 2 3
3 4
2 2
D1
D
4 4
1 2
1 B A2 e
1 1
A Seating Plane A1 L
C
Note: The control dimension is the inch column SYMBOL A A1 A2 B C D D1 e L 0 INCHES MIN 0.055 0.002 0.053 0.012 0.004 0.465 0.390 0.018
0
MILLIMETERS MIN 1.40 0.05 1.35 0.30 0.09 11.80 9.90 0.45 0
0
MAX 0.063 0.006 0.057 0.018 0.008 0.480 0.398 0.030 7
0
MAX 1.60 0.15 1.45 0.45 0.20 12.20 10.10 0.75 70
0.0315 BSC
0.80 BSC
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EXPLANATION OF DATA SHEET REVISIONS: FROM 1.20 TO 1.30 CHANGES DATE
Added and updated Device Status to front page. August 2003 Added 5V tolerant input descriptions. Clarified Programming example D. Clarified SRA, SRB Bit-2 description. Clarified that 5V tolerant inputs are only for devices with top marking of "D2" and newer. Devices with top marking of "CC" or newer do not have 5V tolerant inputs. Clarified that Extended Baud Rate Tables can only be selected via MR0A for both channels. Removed discontinued packages in Ordering Information. Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" to be consistent with JEDEC and Industry norms. Sept 2003
1.30
1.31
1.31
1.32
February 2005
1.32
1.33
August 2005
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet August 2005 Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited. Rev. 1.33
33

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